? semiconductor components industries, llc, 2004 december, 2004 ? rev. 10 1 publication order number: ntd60n02r/d ntd60n02r power mosfet 62 a, 24 v, n?channel, dpak features ? planar hd3e process for fast switching performance ? low r ds(on) to minimize conduction loss ? low c iss to minimize driver loss ? low gate charge ? optimized for high side switching requirements in high?efficiency dc?dc converters ? pb?free packages are available maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit drain?to?source voltage v dss 24 vdc gate?to?source voltage ? continuous v gs 20 vdc thermal resistance junction?to?case total power dissipation @ t c = 25 c drain current continuous @ t c = 25 c, chip continuous @ t c = 25 c, limited by package continuous @ t a = 25 c, limited by wires r jc p d i d i d i d 2.6 58 62 50 32 c/w w a a a thermal resistance junction?to?ambient (note 1) total power dissipation @ t a = 25 c drain current ? continuous @ t a = 25 c r ja p d i d 80 1.87 10.5 c/w w a thermal resistance junction?to?ambient (note 2) total power dissipation @ t a = 25 c drain current ? continuous @ t a = 25 c r ja p d i d 120 1.25 8.5 c/w w a operating and storage temperature t j , and t stg ?55 to 175 c single pulse drain?to?source avalanche energy ? starting t j = 25 c (v dd = 50 vdc, v gs = 10.0 vdc, i l = 11 apk, l = 1.0 mh, r g = 25 ) e as 60 mj maximum lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. when surface mounted to an fr4 board using 0.5 in sq drain pad size. 2. when surface mounted to an fr4 board using the minimum recommended pad size. marking diagram & pin assignments http://onsemi.com y = year ww = work week 60n02r = device code 24 v 8.4 m @ 10 v r ds(on) typ 62 a i d max v (br)dss case 369d dpak (straight lead) style 2 1 gate 3 source 2 drain 4 drain yww t60 n02r yww t60 n02r 1 gate 3 source 2 drain 4 drain 1 2 3 4 see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information n?channel d s g case 369aa dpak (surface mount) style 2 1 2 3 4 1 2 3 4 case 369c dpak (surface mount) style 2 free datasheet http:///
ntd60n02r http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics drain?to?source breakdown voltage (note 3) (v gs = 0 vdc, i d = 250 adc) temperature coefficient (positive) v (br)dss 24 ? 27.5 25.5 ? ? vdc mv/ c zero gate voltage drain current (v ds = 20 vdc, v gs = 0 vdc) (v ds = 20 vdc, v gs = 0 vdc, t j = 150 c) i dss ? ? ? ? 1.5 10 adc gate?body leakage current (v gs = 20 vdc, v ds = 0 vdc) i gss ? ? 100 nadc on characteristics (note 3) gate threshold voltage (note 3) (v ds = v gs , i d = 250 adc) threshold temperature coefficient (negative) v gs(th) 1.0 ? 1.5 4.1 2.0 ? vdc mv/ c static drain?to?source on?resistance (note 3) (v gs = 4.5 vdc, i d = 15 adc) (v gs = 10 vdc, i d = 20 adc) (v gs = 10 vdc, i d = 31 adc) r ds(on) ? ? ? 11.2 8.4 8.2 12.5 10.5 ? m forward transconductance (v ds = 10 vdc, i d = 15 adc) (note 3) g fs ? 27 ? mhos dynamic characteristics input capacitance c iss ? 1000 1330 pf output capacitance (v ds = 20 vdc, v gs = 0 vdc, f = 1.0 mhz ) c oss ? 480 640 transfer capacitance f = 1 . 0 mhz) c rss ? 180 225 switching characteristics (note 4) turn?on delay time t d(on) ? 7.0 ? ns rise time ( v gs = 10 vdc, v dd = 10 vdc, t r ? 33 ? turn?off delay time (v gs = 10 vdc , v dd = 10 vdc , i d = 31 adc, r g = 3.0 ) t d(off) ? 19 ? fall time t f ? 9.0 ? gate charge q t ? 9.5 ? nc (v gs = 4.5 vdc, i d = 31 adc, v ds = 10 vdc ) ( note 3 ) q gs ? 2.2 ? v ds = 10 vdc) (note 3) q gd ? 5.0 ? source?drain diode characteristics forward on?volta g e ( i s = 20 adc , v gs = 0 vdc ) ( note 3 ) v s d ? 0.88 1.2 vdc forward on?voltage (i s = 20 adc , v gs = 0 vdc) (note 3) (i s = 31 adc, v gs = 0 vdc) (i 15 ad v 0vd t 125 c) v sd ? ? 0 . 88 1.15 080 1 . 2 ? vdc (i s 31 adc, v gs 0 vdc) (i s = 15 adc, v gs = 0 vdc, t j = 125 c) ? 0.80 ? reverse recovery time t rr ? 29.1 ? ns (i s = 31 adc, v gs = 0 vdc, di s /dt = 100 a/ s ) ( note 3 ) t a - 13.6 - di s /dt = 100 a/ s) (note 3) t b ? 15.5 ? reverse recovery stored charge q rr ? 0.02 ? c 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures. free datasheet http:///
ntd60n02r http://onsemi.com 3 typical characteristics 10 100 1000 10000 0 6 12 18 2 4 v ds , drain?to?source voltage (v) t j = 100 c t j = 175 c v gs = 0 v 100000 0 20 40 60 80 100 120 0246810 v ds , drain?to?source voltage (v) i d , drain current (a) v gs = 10 v 140 4.5 v 5.0 v 4.0 v 3.8 v 3.6 v 3.4 v 3.2 v 3.0 v 2.8 v 2.8 v 4.2 v 2.4 v 8.0 v 6.0 v 2.6 v t j = 25 c figure 1. on?region characteristics 0.05 2 46 810 r ds(on) , drain?to?source resistance ( ) figure 2. transfer characteristics figure 3. on?resistance versus gate?to?source voltage v gs , gate?to?source voltage (v) v gs , gate?to?source voltage (v) i d = 62 a t j = 25 c 0 0.01 0.02 0.03 0.04 0.05 20 40 60 80 100 120 t j = 25 c v gs = 4.5 v figure 4. on?resistance versus drain current and gate voltage i d , drain current (a) r ds(on) , drain?to?source resistance ( ) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ?50 ?25 0 25 50 75 100 125 150 figure 5. on?resistance variation with temperature t j , junction temperature ( c) r ds(on) , drain?to?source resistance (normalized) figure 6. drain?to?source leakage current versus voltage i dss , leakage (na) 0 20 40 60 80 100 120 02468 t j = ?55 c t j = 25 c t j = 175 c v ds 10 v i d = 31 a v gs = 10 v 0.04 0.03 0.02 0.01 0 i d , drain current (a) v gs = 10 v 140 2.0 175 free datasheet http:///
ntd60n02r http://onsemi.com 4 2000 10 5 0 5 101520 gate?to?source or drain?to?source voltage (v) c, capacitance (pf) t j = 25 c v gs = 0 v c iss c oss c rss c iss v ds = 0 v c rss v gs v ds 1500 1000 500 0 figure 7. capacitance variation q g , total gate charge (nc) figure 8. gate?to?source and drain?to?source voltage versus total charge 1 10 100 1000 1 10 100 r g , gate resistance ( ) figure 9. resistive switching time variation versus gate resistance t, time (ns) v dd = 10 v i d = 31 a v gs = 10 v 1 10 100 0.1 1 10 100 r ds(on) limit thermal limit package limit 10 s 100 s 1 ms 10 ms dc v gs = 20 v single pulse t c = 25 c v ds , drain?to?source voltage (v) i d , drain current (a) 80 0.2 0.4 0.6 0.8 1.0 1.2 figure 10. diode forward voltage versus current v sd , source?to?drain voltage (v) figure 11. maximum rated forward biased safe operating area i s , source current (a) v gs = 0 v t j = 25 c t r t d(off) t f t d(on) 0 1 2 3 4 5 04610 q gs q ds v gs i d = 31 a t j = 25 c 28 v ds , drain?to?source voltage (v) v ds q t 0 4 8 12 16 20 v gs , gate?to?source voltage (v) 70 60 50 40 30 20 10 0 1.4 1.6 1.8 free datasheet http:///
ntd60n02r http://onsemi.com 5 figure 12. thermal response r(t), effective transient thermal resistance (normalized) t, time (s) 0.1 1.0 0.01 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 110 0.1 0.01 0.001 0.0001 0.00001 ordering information order number package shipping 2 ntd60n02r dpak?3 75 units / rail ntd60n02rg dpak?3 (pb?free) 75 units / rail ntd60n02rt4 dpak?3 2500 / tape & reel ntd60n02rt4g dpak?3 (pb?free) 2500 / tape & reel ntd60n02r?001 dpak?3 straight lead 75 units / rail ntd60n02r?1g dpak?3 straight lead (pb?free) 75 units / rail ntd60n02r?032 dpak?3 straight lead (3.2 0.5 mm) 75 units / rail ntd60n02r?032g dpak?3 straight lead (3.2 0.5 mm) (pb?free) 75 units / rail 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifi- cations brochure, brd8011/d. free datasheet http:///
ntd60n02r http://onsemi.com 6 package dimensions dpak case 369c?01 issue o style 2: pin 1. gate 2. drain 3. source 4. drain d a k b r v s f l g 2 pl m 0.13 (0.005) t e c u j h ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.180 bsc 4.58 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* free datasheet http:///
ntd60n02r http://onsemi.com 7 package dimensions d a b r v s f l 2 pl m 0.13 (0.005) t e c u j ?t? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.025 0.035 0.63 0.88 e 0.018 0.024 0.46 0.61 f 0.033 0.045 0.83 1.14 j 0.018 0.023 0.46 0.58 l 0.090 bsc 2.29 bsc r 0.180 0.215 4.57 5.45 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 123 4 dpak case 369aa?01 issue o style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.101 1.6 0.063 6.20 0.244 3.0 0.118 6.172 0.243 mm inches scale 3:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* free datasheet http:///
ntd60n02r http://onsemi.com 8 package dimensions dpak case 369d?01 issue b style 2: pin 1. gate 2. drain 3. source 4. drain 123 4 v s a k ?t? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ntd60n02r/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative. free datasheet http:///
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